Matthew Papakipos
Palo Alto, California
matt-resume@papakipos.com http://www.papakipos.com/Home/matthew-papakipos-s-resume
- Starting & growing startup computer technology companies
- Creating great hardware and software products
- Hiring and managing great engineering teams
- Investing in early-stage technology companies
Career Highlights - Ads: Facebook Local Awareness advertising system
- Mobile networking: Facebook WiFi
- Operating Systems: Chrome OS
- Web browsers: GPU-accelerated browsers & web applications
- Chip design: Programmable GPUs
Entrepreneurship
I start & grow high technology startup companies in Silicon Valley. I excel in hiring top engineering talent, and together conceiving and building innovative products in new categories. I am very comfortable with all stages of startup growth, including financing, hiring, product specification, hardware and software architecture, engineering management, product positioning and launch, evangelism, and press.
Design & Architecture
I architect complex computer systems. I’ve invented and patented a large number of hardware and software algorithms for solving real-world problems. I design systems that are novel, yet practical. I like solving problems that seem impossible to others: making graphics chips programmable (NVIDIA), making browser apps as fast as conventional native apps (NativeClient), making web apps that use graphics hardware (WebGL), creating a new consumer operating system (Chrome OS).
Leadership
I’ve managed both hardware and software project teams, with team sizes up to eighty five people with multiple managers reporting in to me. I’ve recruited and hired hundreds of great engineers, and trained and promoted new engineers and managers and coached them through their first successful projects. I run organizations where I am responsible for setting raises, granting stock options, presenting and writing performance reviews, and developing organizational structure and responsibilities. People who work on my teams often tell me they are the best engineering teams they've been a part of, and we build amazing new products.
Intellectual Property
I’ve filed over seventy patents. I’ve supervised disclosures and filing for hundreds more for my employees. I am well versed in protecting IP through all phases of high technology startup companies. I believe that good products come from novel ideas.
Communication
I’ve negotiated software interface specifications with hardware and software vendors and standards bodies (OpenGL, WebGL, HTML5). I’ve spoken at technical conferences for developers using my products. I am frequently interviewed by technical magazines, industry analysts, and the financial press.
Brown University, Bachelor of Science, Math/Computer Science, 1993.
Stanford University, attended Economics, Math, & CS courses for 2003-2004 academic year. Not enrolled in a degree program.
Palo Alto High School
Employment HistoryPapakipos family investments, 2013-InvestorInvesting capital in a portfolio of venture capital, angel investments, and public markets. Some recent investment theses include: - Investing broadly in global public stock markets, avoiding petrochemical stocks
- Investing in women: female founders, female venture capitalists
- Investing in technology startups with founders who are underrepresented minorities
- Investing in South Korean technology startups
Pied Piper Robotics, 2014-FounderBuilding a new robotics company since 2015. Not saying much publicly about this company yet. Engineering DirectorDeveloped range of projects to connect Facebook more deeply into users' daily lives, including: Worked on various company growth initiatives, including: - Building the Facebook engineering mobile hiring recruiting process, and hiring over 200 iOS and Android engineers.
- Lead the design and deployment of Facebook's iOS and Android training program for engineers making the switch to mobile development.
- Moved the Local Ads & Facebook WiFi teams from Silicon Valley to London.
Engineering DirectorCreated a range of browser, OS, and hardware technologies to make the web richer and a deeper part of daily user application experience. Created new technologies that give browsers and web applications the ability to use CPU & GPU hardware acceleration. This allows developers to create more compelling web applications. - I created and led the Chrome OS project at Google. Created a consumer operating system for netbook computers. Open sourced the software in 2009. Hired the engineering team. The team received a TechCrunch "Crunchie" Award for this work.
- I created and led the Chrome GPU hardware project. Created mechanisms to allow web applications to use GPU hardware accelerated graphics. This includes WebGL and O3D.
- Led the Chrome OS UI team for part of my tenure.
- Led the Chrome HTML5 & APIs team for part of my tenure. These APIs expose the set of hardware and OS capabilities available to web applications in the Chrome web browser. This includes the HTML5 APIs. The APIs launched include: geolocation, offline APIs, rich text editing, WebSockets.
- I started the NativeClient project and helped incubate it through its early days. NativeClient is technology for creating secure web applications that run native C++ code. Filed several of the key early patents.
CTO & occasional Acting VP of Engineering
PeakStream was a Silicon Valley startup company funded by Sequoia Capital, Kleiner Perkins, and Foundation Capital. I founded the company, raised two rounds of venture capital funding, and hired over half of the staff of the company. PeakStream was a leading company developing software environments for multi-core processors and GPUs. As CTO, I was responsible for product architecture, technical leadership, and all technical communication for customers, investors, business partners, and press. Google acquired the company in 2007.
Director of Architecture
I was responsible for the development of hardware architectures for NVIDIA’s graphics chips (GPUs). This included feature selection, hardware design, cmodel development, verification, and developer evangelism. I was responsible for salaries, performance reviews, raises, stock grants, promotions, organizational structure, and external communication for this group. I had four managers reporting to me and a total group size of eighty five people. I was responsible for protecting the IP generated by my group. All of the chip projects below shipped in volume to the mass market in PCs all over the world.
GPU development projects:
- GeForce 6800 Family: Directed our first simultaneous development of three PC GPUs at once, with four managers reporting to me. This architecture is also in the PS3 game console.
- GeForce FX & GeForce FX Go: Led IP review & filing of twenty five patents.
- GeForce 4 & GeForce 4 MX: Directed two managers, launching two GPU chips simulatenously, enhancing profitability substantially.
- GeForce 3 & Quadro 3: Created the first programmable GPU. This architecture is the heart of the XBox game console.
- GeForce 2 & GeForce 2 MX
- GeForce & Quadro: chip architecture & simulation
- TNT & TNT 2: cmodel integration and verification
Engineering process initiatives:
- Linux Server Farm: In 1999, I conceived and designed NVIDIA’s Linux server farm. I saw a tremendous opportunity to save money spent on Sun computers by transitioning our server environment to Linux machines. We rolled it out initially in a cubicle; today it is a server farm of more than 3,000 processors and terabytes of memory and petabytes of disk storage.
- Chip Feature Database: I designed a web-based application for requesting, prioritizing, and managing feature requests for graphics chips. We used this to methodically manage and prioritize the vast number of incoming requests from our developer community and customers.
External communication:
- Negotiated Direct3D graphics APIs with Microsoft, aligning the GeForce 3 perfectly with DirectX 8.
- Created the “Multitexture” extension for OpenGL and achieved ratification of our new standard by the OpenGL ARB standards body, leading NVIDIA’s entry into the OpenGL ARB standards body.
- Spoke at countless game developer events, including GDC.
- Frequently met with top game developers at Id, Valve, Epic, Microsoft and EA to evangelize new product features for games.
Raycer was a startup company that developed a graphics chip for use in the CAD market. I was one of three architects for the Raycer scanline rendering algorithm. I was responsible for making the hardware architecture OpenGL compliant.
I developed UNIX device drivers for the Impact graphics workstation. I architected novel surface tessellation algorithms for the Odyssey graphics workstation.
I developed a system for interactive television presentation and led a small team coding the runtime software for presenting digital television content, including scripting system, graphics display, and input management.
Time Warner Interactive Group, 1994
I developed software for live video effects on Time Warner’s interactive television project. This system performed all the real-time fades, dissolves, wipes, etc. between live video sequences for an interactive shopping application that was deployed in Florida in 1994.
I designed a computer graphics system for offloading traditional optical film effects processing onto a computer system. Due to large dataset sizes, we used the IBM PVS, a 32 processor SMP supercomputer. I was responsible for all of the development of the core image processing algorithms on the supercomputer.
I developed a Mandelbrot Fractal viewer as a demo for this supercomputer. Compared to previous implementations, ours was the first that was fast enough to be honestly called real-time. This demo was avidly used by our sales force in selling the machine. I published a technical paper about the algorithm details, and how to extract maximum performance from the novel hardware architecture of this SIMD supercomputer.
UNIX X Server software development.
As leader of a three student team, I implemented a triangle renderer on the Connection Machine, a 4096 processor supercomputer. Published a Technical Report.
DEC, Palo Alto, 1986 – 1987
UNIX X Server software development.
HP, Cupertino, 1985
UNIX C library validation.
US Patents Issued
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| | 1 | 7,643,030 | | Method and system for efficiently evaluating and drawing NURBS surfaces for 3D graphics | | 2 | 7,570,266 | | Multiple data buffers for processing graphics data | | 3 | 7,508,394 | | Systems and methods of multi-pass data processing | | 4 | 7,477,266 | | Digital image compositing using a programmable graphics processor | | 5 | 7,289,126 | | Gamma-corrected texel storage in a graphics memory | | 6 | 7,274,369 | | Digital image compositing using a programmable graphics processor | | 7 | 7,256,796 | | Per-fragment control for writing an output buffer | | 8 | 7,233,335 | | System and method for reserving and managing memory spaces in a memory resource | | 9 | 7,224,359 | | Depth clamping system and method in a hardware graphics pipeline | | 10 | 7,167,181 | | Deferred shading graphics pipeline processor having advanced features | | 11 | 7,154,507 | | System, method and computer program product for texture shading | | 12 | 7,151,543 | | Vertex processor with multiple interfaces | | 13 | 7,142,215 | | Method and apparatus for processing stencil data using a programmable graphics processor | | 14 | 7,139,003 | | Methods of processing graphics data including reading and writing buffers | | 15 | 7,136,070 | | System, method and computer program product for using an arbitrary quantity as texture address | | 16 | 7,109,999 | | Method and system for implementing programmable texture lookups from texture coordinate sets | | 17 | 7,098,922 | | Multiple data buffers for processing graphics data | | 18 | 7,081,895 | | Systems and methods of multi-pass data processing | | 19 | 7,075,539 | | Apparatus and method for processing dual format floating-point data in a graphics processing system | | 20 | 7,071,947 | | Automatic adjustment of floating point output images | | 21 | 7,064,763 | | Single semiconductor graphics platform | | 22 | 7,053,904 | | Position conflict detection and avoidance in a programmable graphics processor | | 23 | 7,050,055 | | Single semiconductor graphics platform with blending and fog capabilities | | 24 | 7,034,829 | | Masking system and method for a graphics processing framework embodied on a single semiconductor platform | | 25 | 7,015,914 | | Multiple data buffers for processing graphics data | | 26 | 7,002,577 | | Clipping system and method for a single graphics semiconductor platform | | 27 | 6,992,667 | | Single semiconductor graphics platform system and method with skinning, swizzling and masking capabilities | | 28 | 6,950,107 | | System and method for reserving and managing memory spaces in a memory resource | | 29 | 6,906,718 | | Method and system for efficiently evaluating and drawing NURBS surfaces for 3D graphics | | 30 | 6,828,980 | | System, method and computer program product for z-texture mapping | | 31 | 6,774,895 | | System and method for depth clamping in a hardware graphics pipeline | | 32 | 6,771,264 | | Method and apparatus for performing tangent space lighting and bump mapping in a deferred shading graphics processor | | 33 | 6,765,575 | | Clip-less rasterization using line equation-based traversal | | 34 | 6,731,298 | | System, method and article of manufacture for z-texture mapping | | 35 | 6,717,576 | | Deferred shading graphics pipeline processor having advanced features | | 36 | 6,650,331 | | System, method and computer program product for performing a scissor operation in a graphics processing framework embodied on a single semiconductor platform | | 37 | 6,597,363 | | Graphics processor with deferred shading | | 38 | 6,577,309 | | System and method for a graphics processing framework embodied utilizing a single semiconductor platform | | 39 | 6,532,013 | | System, method and article of manufacture for pixel shaders for programmable shading | | 40 | 6,462,737 | | Clipping system and method for a graphics processing framework embodied on a single semiconductor platform | | 41 | 6,342,888 | | Graphics processing unit with an integrated fog and blending operation | | 42 | 6,333,744 | | Graphics pipeline including combiner stages | | 43 | 6,268,875 | | Deferred shading graphics pipeline processor | | 44 | 6,229,553 | | Deferred shading graphics pipeline processor | | 45 | 6,198,488 | | Transform, lighting and rasterization system embodied on a single semiconductor platform |
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US Patent Applications
Papers
Presentations
Press Coverage
Press Coverage at Google
Press Coverage at PeakStream
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