Matthew Papakipos
Palo Alto,
California
matt-resume@papakipos.com
http://www.papakipos.com/work.htm
Expertise
- Starting
& growing startup computer technology companies
- Computer
hardware and software architecture & development
- Interactive
computer graphics
- Mathematical
algorithms & numerical computing
Overview
Entrepreneurship
I start & grow high technology startup companies in Silicon Valley. I excel in hiring top engineering talent,
and together conceiving and building innovative products in new categories. I
am very comfortable with all stages of startup growth, including financing,
hiring, product specification, hardware and software architecture, engineering
management, evangelism, and press.
Design & Architecture
I architect complex computer systems. I’ve invented and
patented a large number of hardware and software algorithms for solving
real-world problems. I excel in using mathematics to tackle hard engineering
problems in novel ways.
Management
I’ve managed both hardware and software project teams, with
team sizes up to eighty five people with multiple managers reporting in to me.
I’ve recruited and hired more than sixty people in the last few years, and
trained and promoted new engineers and managers and coached them through their
first successful projects. I’ve run organizations where I was responsible for
setting raises, granting stock options, presenting and writing performance
reviews, and developing organizational structure and responsibilities.
Intellectual Property
I’ve personally filed over forty patents in the last seven
years. I’ve supervised disclosures and filing for hundreds more for my
employees. I am well versed in protecting IP through all phases of high
technology startup companies.
Communication
I’ve negotiated software interface specifications with
hardware and software vendors and standards bodies. I’ve spoken at technical
conferences for developers using my products. I am frequently interviewed by
technical magazines, industry analysts, and the financial press, from Ars Technica to The Wall St.
Journal.
Brown
University, Bachelor of Science, Math/Computer
Science, 1993.
Stanford University,
attended Economics, Math, & CS courses for 2003-2004 academic year.
Palo Alto High School
Google, 2007-present
Engineering Director
I am presently working on exciting new projects at Google.
CTO & Occasional Acting VP of Engineering
PeakStream was a Silicon
Valley startup company funded by Sequoia Capital, Kleiner Perkins, and Foundation Capital. I founded the
company, raised two rounds of venture capital funding, and hired over half of
the staff of the company. PeakStream was a leading
company developing software environments for multi-core processors. As CTO, I
was responsible for product architecture, technical leadership, and all
technical communication for customers, investors, business partners, and press.
Director of Architecture
I was responsible for the development of hardware
architectures for NVIDIA’s graphics chips (GPUs).
This included feature selection, hardware design, cmodel
development, verification, and developer evangelism and support. I was
responsible for salaries, performance reviews, raises, stock grants,
promotions, organizational structure, and external communication for this
group. I had four managers reporting to me and a total group size of eighty
five people. I was responsible for protecting the IP generated by my group. All
of the chip projects below shipped in volume to the mass market in PCs all over
the world.
GPU development projects:
- GeForce 6800 Family: Directed our first simultaneous
development of three PC GPUs at once, with four
managers reporting to me. This architecture is also in the PS3 game
console.
- GeForce FX & GeForce FX
Go: Led IP review & filing of twenty five patents.
- GeForce 4 & GeForce 4
MX: Directed two managers, launching two GPU chips simulatenously,
enhancing profitability substantially.
- GeForce 3 & Quadro 3:
Created the first programmable GPU. This architecture is the heart of the XBox game console.
- GeForce 2 & GeForce 2 MX
- GeForce & Quadro: chip
architecture & simulation
- TNT
& TNT 2: cmodel integration and verification
Engineering process initiatives:
- Linux
Server Farm: In 1999, I conceived and designed NVIDIA’s Linux server farm.
I saw a tremendous opportunity to save money spent on Sun workstations by
transitioning our server environment to Linux machines. We rolled it out
initially in a cubicle; today it is a server farm of more than 3,000
processors and terabytes of memory and petabytes
of disk storage. I worked closely with the IT group to roll this out to
the whole company. This saved the company many millions of dollars over
the last few years.
- Chip
Feature Database: I designed a web-based application for requesting,
prioritizing, and managing feature requests for graphics chips. We used
this to methodically manage and prioritize the vast number of incoming
requests from our developer community and customers.
External communication:
- Negotiated
Direct3D graphics APIs with Microsoft, aligning the GeForce
3 perfectly with DirectX 8.
- Created
the “Multitexture” extension for OpenGL and
achieved ratification of our new standard by the OpenGL ARB standards
body, leading NVIDIA’s entry into the OpenGL ARB.
- Spoke
at countless developer events, including GDC.
- Frequently
met with top game developers at Id, Valve, Epic, Microsoft and EA to
evangelize new product features for games.
Raycer was a startup company that
developed a graphics chip for use in the CAD market. I was one of three
architects for the Raycer scanline
rendering algorithm. I was responsible for making the hardware architecture
OpenGL compliant.
I developed UNIX device drivers for the Impact graphics
workstation. I architected novel surface tessellation algorithms for the
Odyssey graphics workstation.
I developed a system for interactive television presentation
and led a small team coding the runtime software for presenting digital
television content, including scripting system, graphics display, and input
management.
Time Warner Interactive Group,
1994
I developed software for live video effects on Time Warner’s
interactive television project. This system performed all the real-time fades,
dissolves, wipes, etc. between live video sequences for an interactive shopping
application that was deployed in Florida
in 1994.
I designed a computer graphics
system for offloading traditional optical film effects processing onto a computer
system. Due to large dataset sizes, we used the IBM PVS, a 32 processor SMP
supercomputer. I was responsible for all of the development of the core image
processing algorithms on the supercomputer.
I developed a Mandelbrot
Fractal viewer as a demo for this supercomputer. Compared to previous
implementations, ours was the first that was fast enough to be honestly called
real-time. This demo was avidly used by our sales force in selling the machine.
I published a technical paper about the algorithm details, and how to extract
maximum performance from the novel hardware architecture of this SIMD
supercomputer.
UNIX X Server software
development.
As leader of a three student
team, I implemented a triangle renderer on the
Connection Machine, a 4096 processor supercomputer. Published a Technical
Report.
DEC,
Palo Alto, 1986
– 1987
UNIX X Server software
development.
HP, Cupertino,
1985
UNIX C library validation.
US Patents Issued
|
|
Patent #
|
Patent Title
|
|
1
|
7,167,181
|
Deferred
shading graphics pipeline processor having advanced features
|
|
2
|
7,154,507
|
System,
method and computer program product for texture shading
|
|
3
|
7,151,543
|
Vertex
processor with multiple interfaces
|
|
4
|
7,142,215
|
Method
and apparatus for processing stencil data using a programmable graphics
processor
|
|
5
|
7,139,003
|
Methods
of processing graphics data including reading and writing buffers
|
|
6
|
7,136,070
|
System,
method and computer program product for using an arbitrary quantity as
texture address
|
|
7
|
7,109,999
|
Method
and system for implementing programmable texture lookups from texture
coordinate sets
|
|
8
|
7,098,922
|
Multiple
data buffers for processing graphics data
|
|
9
|
7,081,895
|
Systems
and methods of multi-pass data processing
|
|
10
|
7,075,539
|
Apparatus
and method for processing dual format floating-point data in a graphics
processing system
|
|
11
|
7,071,947
|
Automatic
adjustment of floating point output images
|
|
12
|
7,064,763
|
Single
semiconductor graphics platform
|
|
13
|
7,053,904
|
Position
conflict detection and avoidance in a programmable graphics processor
|
|
14
|
7,050,055
|
Single
semiconductor graphics platform with blending and fog capabilities
|
|
15
|
7,034,829
|
Masking
system and method for a graphics processing framework embodied on a single
semiconductor platform
|
|
16
|
7,015,914
|
Multiple
data buffers for processing graphics data
|
|
17
|
7,002,577
|
Clipping
system and method for a single graphics semiconductor platform
|
|
18
|
6,992,667
|
Single
semiconductor graphics platform system and method with skinning, swizzling and masking capabilities
|
|
19
|
6,950,107
|
System
and method for reserving and managing memory spaces in a memory resource
|
|
20
|
6,906,718
|
Method
and system for efficiently evaluating and drawing NURBS surfaces for 3D
graphics
|
|
21
|
6,828,980
|
System,
method and computer program product for z-texture mapping
|
|
22
|
6,774,895
|
System
and method for depth clamping in a hardware graphics pipeline
|
|
23
|
6,771,264
|
Method
and apparatus for performing tangent space lighting and bump mapping in a
deferred shading graphics processor
|
|
24
|
6,765,575
|
Clip-less
rasterization using line equation-based traversal
|
|
25
|
6,731,298
|
System,
method and article of manufacture for z-texture mapping
|
|
26
|
6,717,576
|
Deferred
shading graphics pipeline processor having advanced features
|
|
27
|
6,650,331
|
System,
method and computer program product for performing a scissor operation in a
graphics processing framework embodied on a single semiconductor platform
|
|
28
|
6,597,363
|
Graphics
processor with deferred shading
|
|
29
|
6,577,309
|
System
and method for a graphics processing framework embodied utilizing a single
semiconductor platform
|
|
30
|
6,532,013
|
System,
method and article of manufacture for pixel shaders
for programmable shading
|
|
31
|
6,462,737
|
Clipping
system and method for a graphics processing framework embodied on a single
semiconductor platform
|
|
32
|
6,342,888
|
Graphics
processing unit with an integrated fog and blending operation
|
|
33
|
6,333,744
|
Graphics
pipeline including combiner stages
|
|
34
|
6,268,875
|
Deferred
shading graphics pipeline processor
|
|
35
|
6,229,553
|
Deferred
shading graphics pipeline processor
|
|
36
|
6,198,488
|
Transform,
lighting and rasterization system embodied on a
single semiconductor platform
|
Pending Patents
I have many more patents pending, both US and international.
Papers
Presentations
Recent Press Coverage
Press Coverage of PeakStream
